Combined resist strip and barrier etch process for dual damascene structures

ABSTRACT

A method of etching a stack is provided. Generally, a trench patterned resist layer is placed over a dielectric layer of the stack. A trench is partially etched into the dielectric layer. A simultaneous stripping of the trench patterned resist layer, etching the barrier layer, and etching the trench is then performed. As a result an etch stack may be provided with less damage. The method may be used to provide a dual damascene structure. The dual damascene structure may be provided by etching a via before placing the trench patterned resist layer over the dielectric layer of the stack.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to the fabrication ofsemiconductor-based devices. More particularly, the present inventionrelates to improved techniques for fabricating semiconductor-baseddevices with dual damascene structures.

[0002] In semiconductor-based device (e.g., integrated circuits or flatpanel displays) manufacturing, dual damascene structures may be used inconjunction with copper conductor material to reduce the RC delaysassociated with signal propagation in aluminum based materials used inprevious generation technologies. In dual damascene, instead of etchingthe conductor material, vias, and trenches may be etched into thedielectric material and filled with copper.

[0003] To facilitate discussion, FIG. 1A is a cross-sectional view of astack 100 on a wafer 110 used in the damascene process of the prior art.A contact 104 may be placed in a dielectric layer 108 over a wafer 110.A barrier layer 112, which may be of silicon nitride or silicon carbide,may be placed over the contact 104 to prevent the copper diffusion. Avia level dielectric layer 116 may be placed over the barrier layer 112.A trench stop layer 120 (silicon carbide or silicon nitride) may beplaced over via level dielectric 116. A trench level dielectric layer124 may be placed over the trench stop layer 120. An ARC layer 128 maybe placed over the trench dielectric layer 124. A patterned resist layer132 may be placed over the hard mask layer 128. The via level dielectriclayer 116 and the trench level dielectric layer 124 may be formed from alow dielectric constant OSG material. The trench etch stop layer 120 andARC layer 128 may be formed from (silicon carbide or silicon nitride fortrench stop layer and SiON for ARC layer).

[0004]FIG. 2 is a high level flow chart of a process used in the priorart to form the stack 100 into dual damascene structure. The stack 100may be subjected to an etch, which etches a via 140 down to the barrierlayer 112 (step 204). The etching of the via 140 may form a crust 144which forms sidewalls. The crust 144 and resist 132 may be removed andrepatterned to form a new resist layer 160, which is patterned to form atrench (step 208), as shown in FIG. 1C. The stack may be subjected to anetch, which etches a trench 164 down to the trench etch stop layer 120(step 212), as shown in FIG. 1D. The etching of the trench 164 may causepart of the via level dielectric layer 116 to facet 172. This facetingmay be considered as damage to the dual damascene structure. The etchingof the trench 164 may also form a new crust 168, which forms sidewalls.The stack 100 may then be subjected to a barrier layer etch (step 216),which opens the via 140 to the copper contact 104, as shown in FIG. 1E.Removal of the barrier material of the barrier layer 112 is a challengeconsidering the poor selectivities between conventional dielectricmaterials and barrier materials. The resist layer 160 and crust 168 maythen be stripped (step 220), to provide the structure shown in FIG. 1F.

[0005] It is desirable to provide an efficient etching process withminimal structure damage.

SUMMARY OF THE INVENTION

[0006] To achieve the foregoing and other objects and in accordance withthe purpose of the present invention for etching a stack. Generally, atrench patterned resist layer is placed over a dielectric layer of thestack. A trench is partially etched into the dielectric layer. Asimultaneous stripping of the trench patterned resist layer, etching thebarrier layer, and etching the trench is then performed. As a result anetch stack may be provided with less damage.

[0007] These and other features of the present invention will bedescribed in more detail below in the detailed description of theinvention and in conjunction with the following figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention is illustrated by way of example, and notby way of limitation, in the figures of the accompanying drawings and inwhich like reference numerals refer to similar elements and in which:

[0009] FIGS. 1A-F are cross-sectional views of a stack on a wafer usedin the damascene process of the prior art.

[0010]FIG. 2 is a high level flow chart of a process used in the priorart to form the stack into dual damascene structure.

[0011]FIG. 3 is a flow chart of a process used in a preferred embodimentof the invention.

[0012] FIGS. 4A-E are cross-sectional views of a stack that is etchedaccording to the preferred embodiment of the invention.

[0013]FIG. 5 is a schematic view of a plasma processing chamber that maybe used in a preferred embodiment of the invention.

[0014]FIG. 6 is a more detailed flow chart of the step of simultaneouslyresist stripping and etching the barrier layer and the trench tocomplete the trench.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The present invention will now be described in detail withreference to a few preferred embodiments thereof as illustrated in theaccompanying drawings. In the following description, numerous specificdetails are set forth in order to provide a thorough understanding ofthe present invention. It will be apparent, however, to one skilled inthe art, that the present invention may be practiced without some or allof these specific details. In other instances, well known process stepsand/or structures have not been described in detail in order to notunnecessarily obscure the present invention.

[0016] To facilitate discussion, FIG. 3 is a flow chart of a processused in a preferred embodiment of the invention. FIG. 4A is across-sectional view of a stack 400 on a wafer 410 used in the dualdamascene process of the preferred embodiment of the invention. Acontact 404 may be placed in a dielectric layer 408 over a wafer 410. Abarrier layer 412, which may be of silicon nitride or silicon carbide,may be placed over the contact 404 to prevent the copper diffusion. Avia level dielectric layer 416 may be placed over the barrier layer 412and the dielectric layer 408. A trench stop layer 420 (silicon carbideor silicon nitride) may be placed over via level dielectric 416. Atrench level dielectric layer 424 may be placed over the trench stoplayer 420. An ARC layer 428 may be placed over the trench dielectriclayer 424. A patterned resist layer 432 may be placed over the hard masklayer 428. The via level dielectric layer 416 and the trench leveldielectric layer 424 may be formed from a low dielectric constant OSGmaterial. The trench etch stop layer 420 and ARC layer 428 may be formedfrom (silicon carbide or silicon nitride for trench stop layer and SiONfor ARC layer). The patterned resist layer 432 may be a photo resistmaterial where the layer 428 is an antireflective coating.

[0017] A via 440 is etched into the stack 400 down to the barrier layer112 (step 304), as shown in FIG. 4B. The etching of the via 440 may forma crust 444 which forms sidewalls. The crust 444 and resist 432 may beremoved and repatterned to form a new resist layer 460, which ispatterned to form a trench (step 308), as shown in FIG. 4C. The stackmay be subjected to an etch, which partially etches a trench 464 down toa level above the trench stop dielectric layer 420 (step 312), as shownin FIG. 4D. The etching of the trench 464 may cause part of the via tofacet 472. This faceting may be considered as damage to the dualdamascene structure. The partial etching of the trench may damage thedual damascene structure within the trench area in other ways. Theetching of the trench 464 may also form a new crust 468, which formssidewalls. The stack 400 is then subjected to a simultaneous resiststrip and etching of the barrier layer 412 and trench to complete thetrench 464 (step 316) to provide the stack 400 shown in FIG. 4E. Thesimultaneous etching of the barrier layer 412 and completion of thetrench 464 may help to etch away the facets 472 and other damage to thetrench area.

[0018]FIG. 5 is a schematic view of a plasma processing chamber 500. Theplasma processing chamber 500 comprising confinement rings 502, an upperelectrode 504, a lower electrode 508, a gas source 510, and an exhaustpump 520. The gas source 510 comprises a stripping gas source 512 and anetching gas source 516. The gas source 510 may comprise additional gassources. Within plasma processing chamber 500, the wafer 410 ispositioned upon the lower electrode 508. The lower electrode 508incorporates a suitable substrate chucking mechanism (e.g.,electrostatic, mechanical clamping, or the like) for holding the wafer410. The reactor top 528 incorporates the upper electrode 504 disposedimmediately opposite the lower electrode 508. The upper electrode 504,lower electrode 508, and confinement rings 502 define the confinedplasma volume. Gas is supplied to the confined plasma volume by gassource 510 and is exhausted from the confined plasma volume through theconfinement rings 502 and an exhaust port by the exhaust pump 520. Afirst RF source 544 is electrically connected to the upper electrode504. A second RF source 548 is electrically connected to the lowerelectrode 508. Chamber walls 552 surround the confinement rings 502, theupper electrode 504, and the lower electrode 508. Both the first RFsource 544 and the second RF source 548 may comprise a 27 MHz powersource and a 2 MHz power source. Different combinations of connecting RFpower to the electrode are possible. In case of Exelan HP made by LAMResearch Corporation™ of Fremont, Calif., that may be used in apreferred embodiment of the invention, both the RF sources are connectedto the lower electrode and the upper electrode is grounded.

[0019]FIG. 6 is a more detailed flow chart of the step of simultaneouslyresist stripping and etching the barrier layer 412 and the trench tocomplete the trench (step 316). The wafer 410 is placed on the lowerelectrode 508, or may already be on the lower electrode 508 for previousprocessing steps. A stripping gas from the stripping gas source 512 iscombined with an etching gas of a fluorine and carbon containing gasfrom the etching gas source 516 are provided by the gas source 510 intothe chamber 500. The gas from the stripping gas source 512 and theetching gas source 510 are used to generate a plasma to simultaneouslystrip the resist layer 460, complete the etch of the trench 464, andetch the barrier layer 412 (step 604). The etching of the barrier layer412 may take on the order of 30 seconds. When the barrier layer 412 iscompletely etched through and the trench 464 etching is completed thegas containing a fluorine and carbon containing etching gas from theetching gas source 516 is discontinued and only the stripping gas isprovided to the plasma, which completes the removal of the resist layer460, without further etching the dielectric material forming the trenchand via and without further etching the barrier layer (step 608).

[0020] In examples of recipes that have been found to be successful insimultaneously stripping the resist, which is a photo resist, andetching the barrier layer and the trench an etching gas containing acarbon source and a fluorine source, such as carbon tetrafluoride CF₄,may be used. Fluorocarbons, hydrofluorocarbons, or mixtures of carbonand fluorine containing gas may be used for the etching gas. Preferablythe etching gas includes Fluorocarbons or hyrdrofluorocarbons. Morepreferably the etching gas comprises CF₄. The Exelan HP may have a firstpower source, which provides a 2 MHz output and a second power sourcewith a 27 MHz output. A medium density plasma with an electron densityof between 10¹¹ to 10⁹ electrons per cm³ may be provided. Morepreferably the electron density may be about 10¹⁰ cm⁻³.

[0021] In an example recipe using O₂/N₂ and CF₄ as an etchant gas, Table1 provides a range of parameters that are preferred in such a process.TABLE 1 MORE BROAD PREFERRED PREFERRED PARAMETERS RANGE RANGE RANGEPressure (mTorr) 100-2000 200-1000 300-360  Power from First Power 0-600  0-300 <50 Source (Watts) Power from Second  50-1200 100-600 200-300  Power Source (Watts) Flow Rate of O₂ 200-6000 400-3000 900-1100(sccm) Flow Rate of N₂  0-1000  0-500 180-220  (sccm) Flow Rate of CF₄ 1-200  1-100 20-60  (sccm)

[0022] In an example recipe using NH₃, N₂, and CF₄ as an etchant gas,Table 2 provides a range of parameters that are preferred in such aprocess. TABLE 2 MORE BROAD PREFERRED PREFERRED PARAMETERS RANGE RANGERANGE Pressure (mTorr) 100-2000 200-1000 300-360 Power from First Power 0-600  0-300 <50 Source (Watts) Power from Second 100-2000 200-1000500-700 Power Source (Watts) Flow Rate of NH₃ 250-6000 500-30001000-2000 (sccm) Flow Rate of N₂  0-600  0-300 <100 (sccm) Flow Rate ofCF₄  1-200  1-100 20-60 (sccm)

[0023] In an example recipe using N₂/H₂ as etchant gases, Table 3provides a range of parameters that are preferred in such a process.TABLE 3 MORE BROAD PREFERRED PREFERRED PARAMETERS RANGE RANGE RANGEPressure (mTorr) 100-2000 200-1000 400-540 Power from First Power 50-2000 100-1000 300-500 Source (Watts) Power from Second  50-2000100-1000 300-500 Power Source (Watts) Flow Rate of H₂ 100-2000 200-1000500-700 (sccm) Flow Rate of N₂ 250-6000 500-3000 1800-2000 (sccm) FlowRate of CF₄  1-200  1-100 20-60 (sccm

[0024] In other embodiments, the via level dielectric layer and thetrench level dielectric layer may be a single dielectric layer. In thealternative the two layers separated by an etch stop layer, even thoughthe trench level dielectric layer is placed over the via leveldielectric layer.

[0025] The etching of a stack using an ammonium and fluorine containinggas as for a plasma source is described in U.S. Patent ApplicationNo.______ (Attorney Docket Number LAM1P157) entitled “Method of EtchingWith NH₃ AND Fluorine Chemistries” by Rao Anapragada and Reza Sadjadi,with the same filing date, and which is incorporated by reference.

[0026] Sidewalls formed by the crust may be removed during the strippingof the resist or may be removed using a separate wet stripping asdescribed in U.S. Patent Application No. ______ (Attorney Docket NumberLAM1P156) entitled “Method of Preventing Damage To Organo-Silicate-GlassMaterials During Resist Stripping” by Rao Anapragada, with the samefiling date, and which is incorporated by reference.

[0027] The invention may reduce damage in a dual damascene structure,which may provide unique dual damascene structure with less damage. Theinvention may be used for etching a trench and barrier to makeelectrical contact with an underlying metal line or a metal contact.

[0028] While this invention has been described in terms of severalpreferred embodiments, there are alterations, permutations, andsubstitute equivalents, which fall within the scope of this invention.It should also be noted that there are many alternative ways ofimplementing the methods and apparatuses of the present invention. It istherefore intended that the following appended claims be interpreted asincluding all such alterations, permutations, and substitute equivalentsas fall within the true spirit and scope of the present invention.

What is claimed is:
 1. A method of etching a stack, wherein the stack comprises a barrier layer and a dielectric layer over the barrier layer, comprising: placing a trench patterned resist layer over the dielectric layer; partially etching a trench in the dielectric layer; and simultaneously stripping the trench patterned resist layer, etching the barrier layer, and completing the etching of the previously partially etched trench.
 2. The method, as recited in claim 1, further comprising: placing a via patterned resist layer over the dielectric layer; etching a via into the dielectric layer; and stripping the via patterned resist layer, wherein the placing a via patterned resist layer, etching the via, and stripping the via pattern resist layer is done before the placing the trench patterned resist.
 3. The method, as recited in claim 2, wherein the etching the via etches the via to the barrier layer.
 4. The method, as recited in claim 3, wherein the simultaneously stripping the trench patterned resist layer, etching the barrier layer, and completing the etching of the previously partially etched trench, comprises: flowing a stripping gas and an etching gas into a plasma chamber; and generating a plasma from the stripping gas and etching gas.
 5. The method, as recited in claim 4, wherein the simultaneously stripping the trench patterned resist layer, etching the barrier layer, and completing the etching of the previously partially etched trench, further comprises stopping the flow of the etching gas so that only stripping gas is flowed into the plasma chamber.
 6. The method, as recited in claim 5, wherein the etching gas comprises a fluorine and carbon containing gas.
 7. The method, as recited in claim 6, wherein the stopping to flow of the etching gas comprises stopping the flow of the fluorine and carbon containing gas.
 8. The method, as recited in claim 1, wherein the simultaneously stripping the trench patterned resist layer, etching the barrier layer, and etching the trench, comprises: flowing a stripping gas and an etching gas into a plasma chamber; and generating a plasma from the stripping gas and etching gas.
 9. The method, as recited in claim 8, wherein the simultaneously stripping the trench patterned resist layer, etching the barrier layer, and etching the trench, further comprises stopping the flow of the etching gas so that only stripping gas is flowed into the plasma chamber.
 10. The method, as recited in claim 9, wherein the etching gas comprises a fluorine and carbon containing gas.
 11. The method, as recited in claim 10, wherein the stopping to flow of the etching gas comprises stopping the flow of the fluorine and carbon containing gas.
 12. An etched stack, wherein the stack comprises a barrier layer and a dielectric layer over the barrier layer, formed by the process comprising: placing a trench patterned resist layer over the dielectric layer; partially etching a trench in the dielectric layer; and simultaneously stripping the trench patterned resist layer, etching the barrier layer, and etching the trench.
 13. The etched stack, as recited in claim 12, wherein the process further comprises: placing a via patterned resist layer over the dielectric layer; etching a via into the dielectric layer; and stripping the via patterned resist layer, wherein the placing a via patterned resist layer, etching the via, and stripping the via patterned resist layer is done before the placing the trench patterned resist.
 14. The etched stack, as recited in claim 13, wherein the etching the via etches the via to the barrier layer.
 15. The etched stack, as recited in claim 14, wherein the simultaneously stripping the trench patterned resist layer, etching the barrier layer, and etching the trench, comprises: flowing a stripping gas and an etching gas into a plasma chamber; and generating a plasma from the stripping gas and etching gas.
 16. The etched stack, as recited in claim 15, wherein the simultaneously stripping the trench patterned resist layer, etching the barrier layer, and etching the trench, further comprises stopping the flow of the etching gas so that only stripping gas is flowed into the plasma chamber.
 17. The method, as recited in claim 16, wherein the etching gas comprises a fluorine and carbon containing gas.
 18. The method, as recited in claim 17, wherein the stopping to flow of the etching gas comprises stopping the flow of the fluorine and carbon containing gas. 